Methods and apparatus for testing isfet arrays

ABSTRACT

The invention provides testing of a chemically-sensitive transistor device, such as an ISFET device, without exposing the device to liquids. In one embodiment, the invention performs a first test to calculate a resistance of the transistor. Based on the resistance, the invention performs a second test to transition the testing transistor among a plurality of modes. Based on corresponding measurements, a floating gate voltage is then calculated with little or no circuitry overhead. In another embodiment, the parasitic capacitance of at least either the source or drain is used to bias the floating gate of an ISFET. A driving voltage and biasing current are applied to exploit the parasitic capacitance to test the functionality of the transistor.

RELATED APPLICATIONS

This application is a divisional application of U.S. application Ser.No. 15/979,439, filed May 14, 2018. U.S. application Ser. No. 15/979,439is a continuation application of U.S. application Ser. No. 13/173,621filed Jun. 30, 2011. U.S. application Ser. No. 13/173,621h claimsbenefit of priority from U.S. Provisional Application No. 61/360,495filed Jul. 1, 2010 and U.S. Provisional Application No. 61/360,493 filedJun. 30, 2010. All applications named in this section are incorporatedherein by reference, each in its entirety.

BACKGROUND

Electronic devices and components have found numerous applications inchemistry and biology (more generally, “life sciences”), especially fordetection and measurement of various chemical and biological reactionsand identification, detection and measurement of various compounds. Onesuch electronic device is referred to as an ion-sensitive field effecttransistor, often denoted in the relevant literature as an “ISFET” (orpHFET). ISFETs conventionally have been explored, primarily in theacademic and research community, to facilitate measurement of thehydrogen ion concentration of a solution (commonly denoted as “pH”).

More specifically, an ISFET is an impedance transformation device thatoperates in a manner similar to that of a MOSFET (Metal OxideSemiconductor Field Effect Transistor), and is particularly configuredto selectively measure ion activity in a solution (e.g., hydrogen ionsin the solution are the “analytes”). A detailed theory of operation ofan ISFET is given in “Thirty years of ISFETOLOGY: what happened in thepast 30 years and what may happen in the next 30 years,” P. Bergveld,Sens. Actuators, 88 (2003), pp. 1-20 (“Bergveld”), which publication ishereby incorporated herein by reference in its entirety.

Details of fabricating an ISFET using a conventional CMOS (ComplementaryMetal Oxide Semiconductor) process may be found in Rothberg, et al.,U.S. Patent Publication No. 2010/0301398, Rothberg, et al., U.S. PatentPublication No. 2010/0282617, and Rothberg et al, U.S. PatentPublication 2009/0026082; these patent publications are collectivelyreferred to as “Rothberg”, and are all incorporated herein by referencein their entirety. In addition to CMOS, however, biCMOS (i.e., bipolarand CMOS) processing may also be used, such as a process that wouldinclude a PMOS FET array with bipolar structures on the periphery.Alternatively, other technologies may be employed wherein a sensingelement can be made with a three-terminal devices in which a sensed ionleads to the development of a signal that controls one of the threeterminals; such technologies may also include, for example, GaAs andcarbon nanotube technologies.

Taking a CMOS example, a P-type ISFET fabrication is based on a p-typesilicon substrate, in which an n-type well forming a transistor “body”is formed. Highly doped p-type (p+) regions S and D, constituting asource and a drain of the ISFET, are formed within the n-type well. Ahighly doped n-type (n+) region B may also be formed within the n-typewell to provide a conductive body (or “bulk”) connection to the n-typewell. An oxide layer may be disposed above the source, drain and bodyconnection regions, through which openings are made to provideelectrical connections (via electrical conductors) to these regions. Apolysilicon gate may be formed above the oxide layer at a location abovea region of the n-type well, between the source and the drain. Becauseit is disposed between the polysilicon gate and the transistor body(i.e., the n-type well), the oxide layer often is referred to as the“gate oxide.”

Like a MOSFET, the operation of an ISFET is based on the modulation ofcharge concentration (and thus channel conductance) caused by a MOS(Metal-Oxide-Semiconductor) capacitance. This capacitance is constitutedby a polysilicon gate, a gate oxide and a region of the well (e.g.,n-type well) between the source and the drain. When a negative voltageis applied across the gate and source regions, a channel is created atthe interface of the region and the gate oxide by depleting this area ofelectrons. For an n-well, the channel would be a p-channel (andvice-versa). In the case of an n-well, the p-channel would extendbetween the source and the drain, and electric current is conductedthrough the p-channel when the gate-source potential is negative enoughto attract holes from the source into the channel. The gate-sourcepotential at which the channel begins to conduct current is referred toas the transistor's threshold voltage V_(TH) (the transistor conductswhen V_(GS) has an absolute value greater than the threshold voltageV_(TH)). The source is so named because it is the source of the chargecarriers (holes for a p-channel) that flow through the channel;similarly, the drain is where the charge carriers leave the channel.

As described in Rothberg, an ISFET may be fabricated with a floatinggate structure, formed by coupling a polysilicon gate to multiple metallayers disposed within one or more additional oxide layers disposedabove the gate oxide. The floating gate structure is so named because itis electrically isolated from other conductors associated with theISFET; namely, it is sandwiched between the gate oxide and a passivationlayer that is disposed over a metal layer (e.g., top metal layer) of thefloating gate.

As further described in Rothberg, the ISFET passivation layerconstitutes an ion-sensitive membrane that gives rise to theion-sensitivity of the device. The presence of analytes such as ions inan analyte solution (i.e., a solution containing analytes (includingions) of interest or being tested for the presence of analytes ofinterest), in contact with the passivation layer, particularly in asensitive area that may lie above the floating gate structure, altersthe electrical characteristics of the ISFET so as to modulate a currentflowing through the channel between the source and the drain of theISFET. The passivation layer may comprise any one of a variety ofdifferent materials to facilitate sensitivity to particular ions; forexample, passivation layers comprising silicon nitride or siliconoxynitride, as well as metal oxides such as silicon, aluminum ortantalum oxides, generally provide sensitivity to hydrogen ionconcentration (pH) in an analyte solution, whereas passivation layerscomprising polyvinyl chloride containing valinomycin provide sensitivityto potassium ion concentration in an analyte solution. Materialssuitable for passivation layers and sensitive to other ions such assodium, silver, iron, bromine, iodine, calcium, and nitrate, forexample, are known, and passivation layers may comprise variousmaterials (e.g., metal oxides, metal nitrides, metal oxynitrides).Regarding the chemical reactions at the analyte solution/passivationlayer interface, the surface of a given material employed for thepassivation layer of the ISFET may include chemical groups that maydonate protons to or accept protons from the analyte solution, leavingat any given time negatively charged, positively charged, and neutralsites on the surface of the passivation layer at the interface with theanalyte solution.

With respect to ion sensitivity, an electric potential difference,commonly referred to as a “surface potential,” arises at thesolid/liquid interface of the passivation layer and the analyte solutionas a function of the ion concentration in the sensitive area due to achemical reaction (e.g., usually involving the dissociation of oxidesurface groups by the ions in the analyte solution in proximity to thesensitive area). This surface potential in turn affects the thresholdvoltage of the ISFET; thus, it is the threshold voltage of the ISFETthat varies with changes in ion concentration in the analyte solution inproximity to the sensitive area. As described in Rothberg, since thethreshold voltage V_(TH) of the ISFET is sensitive to ion concentration,the source voltage V_(S) provides a signal that is directly related tothe ion concentration in the analyte solution in proximity to thesensitive area of the ISFET.

Arrays of chemically-sensitive FETs (“chemFETs”), or more specificallyISFETs, may be used for monitoring reactions—including, for example,nucleic acid (e.g., DNA) sequencing reactions, based on monitoringanalytes present, generated or used during a reaction. More generally,arrays including large arrays of chemFETs may be employed to detect andmeasure static and/or dynamic amounts or concentrations of a variety ofanalytes (e.g., hydrogen ions, other ions, non-ionic molecules orcompounds, etc.) in a variety of chemical and/or biological processes(e.g., biological or chemical reactions, cell or tissue cultures ormonitoring, neural activity, nucleic acid sequencing, etc.) in whichvaluable information may be obtained based on such analyte measurements.Such chemFET arrays may be employed in methods that detect analytesand/or methods that monitor biological or chemical processes via changesin charge at the chemFET surface. Such use of ChemFET (or ISFET) arraysinvolves detection of analytes in solution and/or detection of change incharge bound to the chemFET surface (e.g. ISFET passivation layer).

Research concerning ISFET array fabrication is reported in thepublications “A large transistor-based sensor array chip for directextracellular imaging,” M. J. Milgrew, M. O. Riehle, and D. R. S.Cumming, Sensors and Actuators, B: Chemical, 111-112, (2005), pp.347-353, and “The development of scalable sensor arrays using standardCMOS technology,” M. J. Milgrew, P. A. Hammond, and D. R. S. Cumming,Sensors and Actuators, B: Chemical, 103, (2004), pp. 37-42, whichpublications are incorporated herein by reference and collectivelyreferred to hereafter as “Milgrew et al.” Descriptions of fabricatingand using ChemFET or ISFET arrays for chemical detection, includingdetection of ions in connection with DNA sequencing, are contained inRothberg. More specifically, Rothberg describes using a chemFET array(in particular ISFETs) for sequencing a nucleic acid involvingincorporating known nucleotides into a plurality of identical nucleicacids in a reaction chamber in contact with or capacitively coupled tochemFET, wherein the nucleic acids are bound to a single bead in thereaction chamber, and detecting a signal at the chemFET, whereindetection of the signal indicates release of one or more hydrogen ionsresulting from incorporation of the known nucleotide triphosphate intothe synthesized nucleic acid.

Prior techniques for testing a chemically-sensitive transistor basedarray, such as an ion-sensitive field effect transistor (ISFET) array,included “wet testing.” An ISFET array is sensitive to changes inchemical composition in a fluid. Accordingly, ISFET arrays were commonlytested by flowing one or more liquids over the array (e.g. liquidshaving different pH values), reading out the response for each ISFETelement in the array, and determining whether the element is operatingproperly. Although wet testing has the benefit of testing an ISFET underintended operational conditions, wet testing is considered impracticalin most circumstances.

In particular, wet testing is cumbersome and impractical for high volumemanufacturing. Also, wet testing exposes the device to fluids that maycause corrosion and prevent the device from being fully dried beforenormal operations. Moreover, exposure of the device to liquids maycreate defects in the device or future contamination. For these reasons,once a device is exposed to fluids, a manufacturer will typically notaccept the device.

Accordingly, there is a need in the art for dry testing achemically-sensitive transistor based device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross section of an ion-sensitive field effecttransistor (ISFET).

FIG. 2 illustrates a block diagram of an element array.

FIG. 3 illustrates a simplified flow diagram for testing an elementarray.

FIG. 4 illustrates an example of a 2-T pixel array.

FIG. 5 illustrates an example of a 3-T pixel.

FIG. 6 illustrates a cross section of a floating gate terminaltransistor.

FIG. 7 illustrates a circuit schematic equivalent to a floating gateterminal transistor.

FIG. 8 illustrates a circuit schematic equivalent to a floating gateterminal transistor during a testing phase.

DETAILED DESCRIPTION

Embodiments of the present invention provide a method of testing achemical a chemical detecting device comprised of an array of pixelelements where each pixel element includes a chemically-sensitivetransistor having a source terminal, a drain terminal, and a floatinggate terminal. The method may include connecting of a group of thechemically-sensitive transistors' source terminals in common, applyingfirst test voltages at the source terminals of the group, measuringcorresponding first currents at the drain terminals produced by thefirst test voltages, and calculating resistance values based on thefirst test voltages and currents. The method may also include applyingsecond test voltages at the source terminals of the group to operate thegroup in a different operational mode, wherein the second test voltagesare based at least partially on the resistance values, and measuring acorresponding second set of currents at the drain terminals produced bythe second test voltages. Based on the second test voltages and currentsand operational properties of the chemically-sensitive transistors,calculating a floating gate voltage of each chemically-sensitivetransistor in the group.

Embodiments of the present invention provide a method of dry testing anarray of chemically-sensitive transistors having a source, a drain, anda floating gate. The method may include applying first test voltages toa common source connected group of the chemically-sensitive transistors;calculating a resistance based on the first test voltages and currentsproduced by the first set of test voltages; applying second testvoltages, where the second test voltages drive the chemically-sensitivetransistors to transition among a plurality of operational modes andwhere the second test voltages are based partially on the calculatedresistance; calculating a floating gate voltage of each drivenchemically-sensitive transistor; and determining if each calculatedfloating gate voltage is within a predetermined threshold.

Embodiments of the present invention provide a device including an arrayof chemical detection elements and a testing circuit. Each element mayinclude a chemically-sensitive field effect transistor having asemiconductor body terminal, a source terminal, a drain terminal, and afloating gate terminal. The testing circuit may include a plurality ofdriving voltage terminals at each side of the array where the pluralityof driving voltage terminals coupled to a plurality of source terminalsand a plurality of body terminals, and a current source coupled to thedrain terminal of at least one element in the array to measure a draincurrent by converting the drain current into corresponding voltagemeasurements.

Embodiments of the present invention provide a method of testing atransistor having a floating gate and an overlap capacitance between thefloating gate and at least one of a first and a second terminal. Themethod may include applying a test voltage to the first terminal of thetransistor, biasing a second terminal of the transistor, measuring anoutput voltage at the second terminal, and determining if the outputvoltage is within a predetermined range. The test voltage via theoverlap capacitance may place the transistor into an active mode.

Embodiments of the present invention provide a device including an arrayof detection elements and a test circuit. Each element may include afield effect transistor having a floating gate, a first terminal, asecond terminal, and an overlap capacitance between the floating gateand at least one of the first and second terminals. The testing circuitmay include a driving voltage terminal coupled to at least one firstterminal, a biasing current terminal coupled to at least one secondterminal, and an output voltage measurement terminal coupled to the atleast one second terminal.

Embodiments of the present invention relate to a system and method fortesting ion-sensing devices such as an ISFET device. Typically, ISFETssense changes in the chemical composition in micro-wells that are formedabove the ISFET. Such chemical changes may be caused by chemicalreaction in fluids contained in the micro-wells. FIG. 1 is a simplifieddiagram of an ISFET 100. ISFET 100 is illustrated as an NMOS device;however, a PMOS device may also be used in aspects of the presentinvention. In this embodiment, the ISFET 100 is a semiconductor devicewith four terminals. The four terminals are a gate terminal 110, a drainterminal 120, a source terminal 130, and a body terminal 140. The gateterminal 110 may be a floating gate.

The ISFET 100 may include a floating gate with a micro-well above thefloating gate. This micro-well may contain an oxide (or other materials)with surface sites that cause a specific ion species to bind, inducing achange in charge distribution, and causing a change in potential at thesurface. This change in surface potential may then be detected by theISFET and measured by a read circuit, and represents the amount of ionscontained within the micro-well. It is in this way that each ISFET in anarray (e.g., ISFET element array 210 of FIG. 2) can be used to detectlocal variations in ion concentration of a sample liquid that ispresented over the array.

The ISFET 100 may operate similar to a standard MOSFET device and maytransition among a few operational regions. When the ISFET 100 is biasedsuch that V_(GS)−V_(th) is positive and greater than V_(DS), thetransistor is in the triode region, which is also commonly referred toas the linear region. In the triode region, the current through thedrain terminal 120, I_(D), may be defined as:

$\begin{matrix}{I_{D} = {\mu_{n}C_{ox}\frac{W}{L}\left( {{\left( {V_{GS} - V_{th}} \right)V_{DS}} - \frac{V_{DS}^{2}}{2}} \right)}} & {{Triode}\mspace{14mu}{Region}\mspace{14mu}{Equation}}\end{matrix}$

where μ_(n) is a charge-carrier effective mobility coefficient, C_(ox)is a gate oxide capacitance per unit area coefficient, W is a gatewidth, L is a gate length, V_(GS) is a voltage between the gate andsource terminals, V_(th) is the threshold voltage, and V_(DS) is thevoltage between the drain and source terminals. In the triode region,the transistor has ohmic behavior between the drain and source and thedrain current does not saturate.

When V_(GS)−V_(th) is positive and less than V_(DS), the ISFET 100operates in the saturation region, which is also commonly referred to asthe active region. In the saturation region, the current through thedrain terminal 120, I_(D), may be defined as:

$\begin{matrix}{I_{D} = {\frac{\mu_{n}C_{ox}}{2}\frac{W}{L}\left( {V_{GS} - V_{th}} \right)^{2}\left( {1 + {\lambda\; V_{DS}}} \right)}} & {{Saturation}\mspace{14mu}{Region}\mspace{14mu}{Equation}}\end{matrix}$

where μ_(n) is the charge-carrier effective mobility coefficient, C_(ox)is the gate oxide capacitance per unit area coefficient, W is the gatewidth, L is the gate length, V_(GS) is the voltage between the gate andsource terminals, V_(th) is the threshold voltage, V_(DS) is the voltagebetween the drain and source terminals, and λ the factor for channellength modulation.

The ISFET 100 also has a threshold voltage dependent on the bulkpotential. The bulk potential is referred to as the body voltage atterminal 140 and may operate as a second gate. The body effect may bedefined as:

V _(TN) =V _(TO)+γ(√{square root over (V _(SB)+2ϕ)}−√{square root over(2ϕ)})  Body Effect Equation

where V_(TN) is a threshold voltage with substrate bias present, V_(TO)is a zero-V_(SB) value of threshold voltage, V_(SB) is a voltage betweenthe source and body terminals, γ is a body effect parameter, and 2ϕ is asurface potential parameter.

The ISFET 100 may be placed in a pixel element, and the pixel elementmay be a part of an array. FIG. 2 illustrates a device 200 with an ISFETelement array 210. Each element in the array 210 may include an ISFET asdescribed above in FIG. 1 and may also include other transistors andelectrical components. The array 210 may be arranged as a plurality ofrows and columns. The array 210 may also have ISFET terminal connectionsat both ends of the columns and both sides of the rows, and, thus, mayhave ISFET terminal connections at each of the four edges of the array210. The body connection may be set to a bias voltage. For example, eachedge may have source connections of the ISFET in the array 210 asdescribed below.

The array 210 is typically large and thus the source resistance alongthe array may vary by the inherent resistance of the transistor well andconnection to the source. In an embodiment of the present invention, theISFET array 210 may be tested by strategically placing body and sourceconnections access at different physical locations around the array.Resistance of the source connections may then be calibrated to determinean accurate representation of the desired floating gate voltage.

FIG. 3 illustrates a simplified flow diagram of a method 300 to test anISFET array, without the presence of fluids in contact with or adjacentto the array, according to an embodiment of the present invention.Initially, the device may be entered into a test mode where the devicecircuitry may connect the sources of all the ISFETs in common (i.e., allof the ISFET sources are connected together) (Step 310). In anotherembodiment, the array circuitry may connect the sources of alternaterows or columns in common (e.g., the sources of odd numbered rowsconnected together and the sources of even numbered rows connectedtogether). The alternate rows or column arrangement may be a structuralarray testing technique to allow the test procedure to test theintegrity of the arrays of the rows and columns. For example, thepresence of column defects (e.g., two columns are shorted together dueto a manufacturing defect) may be tested by driving odd columns (but noteven columns) high (e.g. by applying a voltage) and measuring the evencolumns to see whether the even columns stay low. If an even columnmeasures high, this identifies a defective column. For row testing, onerow may be driven and the other side of the row may measured to ensurethat the signal passes across the array. Thus, structural array testingmay test the connectivity of rows and columns in the array. In additionto connecting the sources of ISFETs in the array as desired, other orsimilar connections to drains of the ISFETs may also be established.

After the source connections are made, a first test may be performed(Step 320). In the first test, first test voltages may be forced(applied) through the array. The first test voltages may be applied atmultiple sides of the device such as either end of the columns or eitherside of the rows in the array. For example, the first test voltages maybe applied to each of the sides sequentially. The first test voltagesmay be applied to the body and source terminals of the connected ISFETs.The first test voltages may include an initial voltage sweep to identifya suitable operating (or bias) voltage to test the pixel array.

First test measurements corresponding to the first test may then beobtained (Step 330). The first test voltages may produce correspondingcurrents through each connected ISFET. The produced currents may then bemeasured. A range of different voltage and current measurements may beprovided in the embodiments of the present invention. For example,source and drain voltages may be forced while setting the body to a biasvoltage of either an analog supply voltage or analog ground (dependingon whether the ISFET is a PMOS or NMOS device). The resultant draincurrent may then be measured by a current source converting the measuredcurrent into a corresponding voltage value. In another example, thebody, in principle, may be set to a voltage between the analog supplyvoltage and analog ground. Further, all body terminals may be set to thesame voltage in an ISFET array and, thus, all the ISFETS in the arraymay be similarly biased. Another test may characterize threshold voltagemismatches across the array.

Based on the first test voltage values and the corresponding measuredcurrents, a resistance value for the source connections may becalculated (Step 340). For example, a resistance gradient for the sourceconnections may be calculated showing the resistance relationship of thetest voltages and measured currents.

After calculating a resistance value for the source connections, bodyand source connections relative to one side of the device (e.g., one endof the columns) may be established. A second test may then be performed(Step 350). In the second test, second test voltages and currents may beforced or applied through the array. The second test voltages may be avoltage sweep at different operating (or bias) voltage points. Hence,the body connection, which is a bias voltage, may be set accordingly.The second test voltages and currents may be a sweep of a range ofvoltages that will operate the ISFETs in a different operational mode asdescribed above, such as triode mode and saturation mode. Further, theISFETs may be operated in body effect mode by using the body terminal asa second gate.

Second test measurements corresponding to the second test may then beobtained (Step 360). In each iteration of forcing or applying the secondtest voltages and currents, different currents and voltages as seen onthe array may be measured. For example, source and drain voltages may beforced while the body voltage ranges between the analog supply voltageand analog ground voltage. The produced drain currents may be measuredby a current source that may convert the current into correspondingvoltage values. Based on the forced and measured voltages and currents,the gate voltage of the ISFETs may be calculated (Step 370).Specifically, the operational equations of the different modes describedabove may be used to calculate the gate voltage based on the forced andmeasured voltages and currents. Thus, the gate voltage for each ISFETelement may be calculated to determine if the ISFET is working properly.

In an embodiment, steps 350-370 may be repeated for one or more othersides of the device (such as, e.g., the opposite end of the column). Inanother embodiment, steps 350-370 may be repeated after increasing ordecreasing the forced voltages and currents by a factor of, for example,two. The gate voltage may then be calculated from the adjusted voltage(the bias point). The increased or decreased iteration may also berepeated for one or more other sides of the device. Also, the increasingor decreasing iteration may be repeated multiple times, each time inwhich the forced voltages and currents are adjusted by some factor witheach iteration. After all iterations are complete, the calculated gatevoltages may be averaged together to obtain a more accuraterepresentation of the ISFET gate voltage. The averaged gate voltage maythen be compared to a desired threshold range to determine if each ISFETis working properly. Further, the location (e.g., X and Y column and rowin the array), values for each ISFET gate voltage, and/or the workingcondition of each ISFET may be recorded in a register, for example.Additional circuitry may be provided to allow for programming and/orerasing of each pixel element where the floating gate voltage of eachISFET may be programmed and/or erased. In some embodiments, theprogram/erase capability may provide a higher level of fault detectioncoverage. However, the program/erase circuitry may operate on a highervoltage than other circuit components, and design techniques to isolatehigher voltage circuits may need to be applied to ensure circuitcomponents are not damaged.

In another embodiment, in addition to voltage and current, thetemperature of the device may also be varied to modulate the thresholdvoltage of the ISFET element. By varying the temperature, alternate datapoints may be observed and used to calculate the gate voltage of theISFET element.

Further, the circuitry for individual pixel elements may take a varietyof different forms. FIG. 4 illustrates a two-transistor (2-T) pixelarray 400 showing 4 pixel elements that may be used in aspects of thepresent invention. The pixel array 400 may include a plurality of pixelelements 401.1-401.n. Each pixel element 401 may include an ISFET 410and another transistor 420. In a 2-T pixel embodiment, the array may betested by controlling and/or measuring all nodes except the floatinggate terminal of the ISFET.

FIG. 5 illustrates a three-transistor (3-T) pixel element 500 that maybe used in aspects of the present invention. The pixel element 500 mayinclude an ISFET 510, and two other transistors 520, 530. In a 3-T pixelembodiment, the array may be tested by controlling and/or measuring allnodes except the floating gate terminal of the ISFET. The I-Sink may bea controllable current source to provide a constant current to theISFET. In this embodiment, the I Sink capability adds anothermeasurement point that may be used to more accurately calculate the gatevoltage. Other variations of the pixel circuitry may be used with theembodiments of the present invention.

The dry testing embodiments of the present invention described aboveexploit the characteristics of a floating gate transistor to test thefunctionality of the floating gate transistor. Therefore, the operationof the device can be tested with little to no circuit overhead, and thearray size can be optimized because additional test circuitry is notrequired in the array area. Moreover, embodiments of the presentinvention do not require liquid to fully test the array; therefore,possible contamination is avoided.

Although aspects of the present invention have been described in whichan ISFET array may be tested without the use of liquids, aspects of thepresent invention may be employed in conjunction with the use of liquidsfor testing purposes. For example, liquids having a known pH may beapplied before, during, or after the dry testing techniques describedherein. Thus, dry testing techniques described herein may be usedtogether with wet testing techniques, if desired.

Moreover, different embodiments of the present invention herein havebeen described using an ISFET. However, the present invention is notlimited to ISFETs and may be applicable to other suitable floating gatetransistor devices or other suitable chemically-sensitive transistors.

In another embodiment of the present invention, the parasiticcapacitances coupled to the floating gate may be used to test thefunctionality of a floating gate transistor. FIG. 6 shows a simplifieddiagram of a floating gate transistor 600 such as an ISFET. Thetransistor 600 may include a floating gate 612, a drain 614, and asource 616. In this embodiment, the drain 614 and source 616 may bep-type implants within an n-type substrate, thus forming a p-channel FETdevice. However, it will be understood by those skilled in the art thatthe transistor 600 may be formed using an n-channel FET device havingits drain and source formed using n-type implants within a p-typesemiconductor.

An ISFET may be formed, generally, using a self-aligned process. Apolysilicon gate may be formed, and floating gate 612 may be formed on agate oxide 615 or other suitable gate insulator. Source and drainimplants may be made in several steps. Before a nitride spacer isapplied, an LDD (lightly doped drain) implant may be made. The LDDimplant diffuses a small distance under the gate to reduce the electricfield and to reduce the negative aspects of transistor performance suchas hot carriers. The LDD implant, along with a step of degenerativedoped implantation, forms the drain 614 and the source 616. The drain614 and source 616 may have partially overlapping portions 607, 608arranged under respective portions of gate oxide 615. The overlappingportions 607, 608 are formed within their respective implants such thata portion of the implants are beneath the floating gate electrodecreating a parasitic capacitance. A process parameter relating to sizeof the overlap portions may be adjusted to control the size of theoverlap portion and their capacitance.

FIG. 7 shows a circuit schematic equivalent to transistor 600illustrating parasitic capacitance between the gate and source (C_(GS))and parasitic capacitance between the gate and drain (C_(GD)).Alternatively, parasitic capacitance may exist between the gate anddrain only or between the gate and source only.

In an embodiment of the present invention, a floating gate transistormay be tested using the above-described parasitic capacitance withoutusing a fluidic bias to operate the floating gate. FIG. 8 illustrates afloating gate transistor test structure for a pixel element in an arrayaccording to an embodiment of the present invention. The floating gatetransistor (e.g. an ISFET) of FIG. 8 is arranged in a source followerconfiguration; however, it will be understood by those skilled in theart that other configurations are applicable such as common source. Thedrain of the floating gate transistor may be coupled to a voltage powersupply, V_(DD), to drive the transistor. V_(DD), for example, may be 3volts. The source of the floating gate transistor may be biased with acurrent source. For example, the current source may be a 1 μA currentsource.

The voltage at the source (shown as V_(OUT) in FIG. 8) may then bemeasured. The source voltage V_(OUT) may be representative of thevoltage on the floating gate. The parasitic capacitance of thetransistor forces the floating gate into the saturation region and,thus, the transistor may produce source voltage V_(OUT), which followsthe gate potential of interest. The transistor's threshold voltage andparasitic capacitance values may be designed to allow the propercoupling to the floating gate that is sufficient to bring the transistorinto its operational range.

If the source voltage V_(OUT) is within an expected range of a normaldistribution of the array, the pixel may be considered operationalbecause the test determines that the floating gate transistor canproduce a valid and measurable signal. However, if the measured signalis too high or too low as compared to the normal distribution, it mayindicate that an excessive trapped charge may be present at the floatinggate. Also, if the distribution of the measured values in the testedarray is significantly wide, it may indicate a large non-uniformity ofthe individual pixel elements. Large non-uniformities are generallyconsidered unreliable and, thus, the array may be unusable.

In another embodiment, the floating gate transistor test may be expandedto measure the gain of the pixel and/or to determine other pixelproperties. Again, the test may be conducted without using a fluidicbias to operate the floating gate and, therefore, maintaining theintegrity of the array.

In an embodiment, the drain voltage may be varied while measuringcorresponding source voltages. The source biasing current may heldconstant while the drain voltage is varied. In a first step, a firstvoltage may be applied to the drain, for example 3V, and the source maybe biased accordingly. In a second step, the drain voltage may beadjusted to a second voltage, for example 2.8V, while the bias currentat the source is held constant from the first step. The correspondingsource voltage may be measured. The difference in the drain voltage (200mV in the example) couples to the floating gate because of the overlapcapacitance C_(GD). The resulting source voltage may thus be a fractionof the drain voltage difference. The ratio of the measured value to theinput voltage represents the pixel gain and may be used to ascertainother pixel properties of interest.

Several embodiments of the present invention are specificallyillustrated and described herein. However, it will be appreciated thatmodifications and variations of the present invention are covered by theabove teachings. In other instances, well-known operations, componentsand circuits have not been described in detail so as not to obscure theembodiments. It can be appreciated that the specific structural andfunctional details disclosed herein may be representative and do notnecessarily limit the scope of the embodiments.

Those skilled in the art may appreciate from the foregoing descriptionthat the present invention may be implemented in a variety of forms, andthat the various embodiments may be implemented alone or in combination.Therefore, while the embodiments of the present invention have beendescribed in connection with particular examples thereof, the true scopeof the embodiments and/or methods of the present invention should not beso limited since other modifications will become apparent to the skilledpractitioner upon a study of the drawings, specification, and followingclaims.

Various embodiments may be implemented using hardware elements, softwareelements, or a combination of both. Examples of hardware elements mayinclude processors, microprocessors, circuits, circuit elements (e.g.,transistors, resistors, capacitors, inductors, and so forth), integratedcircuits, application specific integrated circuits (ASIC), programmablelogic devices (PLD), digital signal processors (DSP), field programmablegate array (FPGA), logic gates, registers, semiconductor device, chips,microchips, chip sets, and so forth. Examples of software may includesoftware components, programs, applications, computer programs,application programs, system programs, machine programs, operatingsystem software, middleware, firmware, software modules, routines,subroutines, functions, methods, procedures, software interfaces,application program interfaces (API), instruction sets, computing code,computer code, code segments, computer code segments, words, values,symbols, or any combination thereof. Determining whether an embodimentis implemented using hardware elements and/or software elements may varyin accordance with any number of factors, such as desired computationalrate, power levels, heat tolerances, processing cycle budget, input datarates, output data rates, memory resources, data bus speeds and otherdesign or performance constraints.

Some embodiments may be implemented, for example, using acomputer-readable medium or article which may store an instruction or aset of instructions that, if executed by a machine, may cause themachine to perform a method and/or operations in accordance with theembodiments. Such a machine may include, for example, any suitableprocessing platform, computing platform, computing device, processingdevice, computing system, processing system, computer, processor, or thelike, and may be implemented using any suitable combination of hardwareand/or software. The computer-readable medium or article may include,for example, any suitable type of memory unit, memory device, memoryarticle, memory medium, storage device, storage article, storage mediumand/or storage unit, for example, memory, removable or non-removablemedia, erasable or non-erasable media, writeable or re-writeable media,digital or analog media, hard disk, floppy disk, Compact Disc Read OnlyMemory (CD-ROM), Compact Disc Recordable (CD-R), Compact DiscRewriteable (CD-RW), optical disk, magnetic media, magneto-opticalmedia, removable memory cards or disks, various types of DigitalVersatile Disc (DVD), a tape, a cassette, or the like. The instructionsmay include any suitable type of code, such as source code, compiledcode, interpreted code, executable code, static code, dynamic code,encrypted code, and the like, implemented using any suitable high-level,low-level, object-oriented, visual, compiled and/or interpretedprogramming language.

What is claimed is:
 1. A device, comprising: an array of chemicaldetection elements, each element including: a chemically-sensitive fieldeffect transistor having a semiconductor body terminal, a sourceterminal, a drain terminal, and a floating gate terminal; and a testingcircuit including: a plurality of driving voltage terminals at each sideof the array, the plurality of driving voltage terminals coupled to aplurality of source terminals and a plurality of body terminals; acurrent source coupled to the drain terminal of at least one element inthe array to measure a drain current by converting the drain currentinto corresponding voltage measurements.
 2. The device of claim 1,wherein the chemically-sensitive transistor is an ISFET.
 3. The deviceof claim 1, wherein the testing circuit is configured to drive thechemically-sensitive field effect transistors to operate in differentmodes.
 4. The device of claim 3, wherein the different modes includetriode mode and saturation mode.
 5. A device, comprising: an array ofdetection elements, each element including: a field effect transistorhaving a floating gate, a first terminal, a second terminal, and anoverlap capacitance between the floating gate and at least one of thefirst and second terminals; and a testing circuit including: a drivingvoltage terminal coupled to at least one first terminal, a biasingcurrent terminal coupled to at least one second terminal, and an outputvoltage measurement terminal coupled to the at least one secondterminal.
 6. The device of claim 5, wherein each field effect transistoris an ISFET.
 7. The device of claim 5, wherein the first terminal ofeach field effect transistor is a drain terminal and the second terminalof each field effect transistor is a source terminal.
 8. The device ofclaim 5, wherein the overlap capacitance is formed by a gate oxide layermaterial that partially overlaps a terminal implant of the transistor.